View CXK77B1840AGB_278976.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SONY(R)
Description
CXK77B3640AGB / CXK77B1840AGB
37/38/4/45
Preliminary
4Mb Late Write HSTL High Speed Synchronous SRAMs (128K x 36 or 256K x 18 Organization)
The CXK77B3640A (organized as 131,072 words by 36 bits) and the CXK77B1840A (organized as 262,144 words by 18 bits) are high speed BiCMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input registers, high speed RAM, output registers/latches, and a one-deep write buffer onto a single monolithic IC. Four distinct read operation protocols, Register - Register (R-R), Register - Latch (R-L), Register - Flow Thru (R-FT), and Dual Clock (DC), and one write operation protocol, Late Write (LW), are supported, providing a flexible, high-performance user interface. All address, data, and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the positive edge of K clock. Read operation protocol is selectable through external mode pins M1 and M2. Write operations are internally self-timed, eliminating the need for complex off-chip write pulse generation. In Register - Latch and Register - Flow Thru modes, when SW (Global Write Enable) is driven active, the subsequent positive edge of K clock tristates the SRAM's output drivers immediately, allowing Read-Write-Read operations to be initiated consecutively, with no dead cycles between them. The output drivers are series terminated, and the output impedance is programmable through an external impedance matching resistor RQ. By connecting RQ between ZQ and V SS, the output impedance of all DQ pins can be precisely controlled. Sleep (power down) mode control is provided through the asynchronous ZZ input. 270 MHz operation is obtained from a single 3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.
Features
* Fast Cycle / Access Time ---------------------------------37 -38 -4 -45 R-R Mode tKHKH / tKHQV -----------------3.45ns / 2.25ns 3.8ns / 2.25ns 3.8ns / 2.25ns 5.0ns / 2.50ns R-L, R-FT Modes tKHKH / tKHQV -----------------4.8ns / 4.6ns 4.8ns / 4.8ns 5.2ns / 5.2ns 6.0ns / 6.0ns **DC Mode** tKHKH / tKHQV -----------------3.7ns / 4.9ns 3.8ns / 4.9ns 4.0ns / 5.2ns 4.5ns / 6.0ns
Note: Contact Sony Memory Marketing for availability of DC mode functionality in CXK77B1840A. * Single 3.3V power supply (VDD): 3.3V 5% * Register - Register (R-R), Register - Latch (R-L), Register - Flow Thru (R-FT), or Dual Clock (DC) read operations * Read operation protocol selectable via dedicated mode pins (M1, M2) * Fully coherent, late write, self-timed write operations * Byte Write capability * Differential input clocks (K/K, C/C) * Asynchronous output enable (G) * Dedicated output supply voltage (VDDQ): 1.5V typical, 2.0V maximum * HSTL-compatible I/O interface with dedicated input reference voltage (VREF): 0.75V typical * Programmable impedance output drivers * Sleep (power down) mode via dedicated mode pin (ZZ) * JTAG boundary scan (subset of IEEE standard 1149.1) * 119 pin (7x17), 1.27mm pitch, 14mm x 22mm Plastic Ball Grid Array (PBGA) package
4Mb, Sync LW, HSTL, rev 1.5
1 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB 128K x 36 Pin Assignment (Top View) 1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQ7c DQ5c VDDQ DQ2c DQ0c VDDQ DQ0d DQ2d VDDQ DQ5d DQ7d NC NC VDDQ
Preliminary
2
SA6 NC (3) SA12 DQ8c DQ6c DQ4c DQ3c DQ1c VDD DQ1d DQ3d DQ4d DQ6d DQ8d SA10 NC (1) TMS
3
SA7 SA8 SA5 VSS VSS VSS SBWc VSS VREF VSS SBWd VSS VSS VSS M1 SA9 TDI
4
NC NC VDD ZQ SS G C C VDD K K SW SA14 SA11 VDD SA16 TCK
5
SA3 SA4 SA0 VSS VSS VSS SBWb VSS VREF VSS SBWa VSS VSS VSS M2 SA1 TDO
6
SA2 NC (2) SA13 DQ8b DQ6b DQ4b DQ3b DQ1b VDD DQ1a DQ3a DQ4a DQ6a DQ8a SA15 NC (1) NC
7
VDDQ NC NC DQ7b DQ5b VDDQ DQ2b DQ0b VDDQ DQ0a DQ2a VDDQ DQ5a DQ7a NC ZZ VDDQ
Notes: 1. Pad Locations 2T and 6T are true no-connects. However, they are defined as SA address inputs in x18 LW SRAMs. 2. Pad Location 6B is a true no-connect. However, it is defined as an SA address input in 8Mb and 16Mb LW SRAMs. 3. Pad Location 2B is a true no-connect. However, it is defined as an SA address input in 16Mb LW SRAMs.
4Mb, Sync LW, HSTL, rev 1.5
2 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB 256K x 18 Pin Assignment (Top View) 1 A B C D E F G H J K L M N P R T U
VDDQ
Preliminary
2
SA6
3
SA7
4
NC
5
SA3
6
SA2
7
VDDQ
NC NC DQ0b NC (1b) VDDQ NC (1b) DQ3b VDDQ NC (1b) DQ5b VDDQ DQ7b NC (1b) NC NC VDDQ
NC (3) SA12 NC (1b) DQ1b NC (1b) DQ2b NC (1b) VDD DQ4b NC (1b) DQ6b NC (1b) DQ8b SA10 SA17 TMS
SA8 SA5 VSS VSS VSS SBWb VSS VREF VSS VSS VSS VSS VSS M1 SA9 TDI
NC VDD ZQ SS G C C VDD K K SW SA14 SA11 VDD NC (1a) TCK
SA4 SA0 VSS VSS VSS VSS VSS VREF VSS SBWa VSS VSS VSS M2 SA1 TDO
NC (2) SA13 DQ8a NC (1b) DQ6a NC (1b) DQ4a VDD NC (1b) DQ2a NC (1b) DQ1a NC (1b) SA15 SA16 NC
NC NC NC (1b) DQ7a VDDQ DQ5a NC (1b) VDDQ DQ3a NC (1b) VDDQ NC (1b) DQ0a NC ZZ VDDQ
Notes: 1a. Pad Location 4T is a true no-connect. However, it is defined as an SA address input in x36 LW SRAMs. 1b. Pad Locations 2D, 7D, 1E, 6E, 2F, 1G, 6G, 2H, 7H, 1K, 6K, 2L, 7L, 6M, 2N, 7N, 1P, and 6P are true no-connects. However, they are defined as DQ data inputs / outputs in x36 LW SRAMs. 2. Pad Location 6B is a true no-connect. However, it is defined as an SA address input in 8Mb and 16Mb LW SRAMs. 3. Pad Location 2B is a true no-connect. However, it is defined as an SA address input in 16Mb LW SRAMs.
4Mb, Sync LW, HSTL, rev 1.5
3 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB Pin Description
Preliminary
Symbol SA DQa, DQb DQc, DQd
Type Input I/O
Description Synchronous Address Inputs - Registered on the rising edge of K. Synchronous Data Inputs / Outputs - Registered on the rising edge of K during write operations. DQa - indicates Data Byte a DQb - indicates Data Byte b DQc - indicates Data Byte c DQd - indicates Data Byte d Differential Input Clocks Differential Output Control Clocks - For Dual-Clock read operations only. Synchronous Select Input - Registered on the rising edge of K. SS = 0 specifies a Write Operation when SW = 0 specifies a Read Operation when SW = 1 SS = 1 specifies a Deselect Operation Synchronous Global Write Enable Input - Registered on the rising edge of K. SW = 0 specifies a Write Operation when SS = 0 SW = 1 specifies a Read Operation when SS = 0 Synchronous Byte Write Enable Inputs - Registered on the rising edge of K. SBWa = 0 specifies write Data Byte a when SS = 0 and SW = 0 SBWb = 0 specifies write Data Byte b when SS = 0 and SW = 0 SBWc = 0 specifies write Data Byte c when SS = 0 and SW = 0 SBWd = 0 specifies write Data Byte d when SS = 0 and SW = 0 Asynchronous Output Enable Input - De-asserted (high) forces the data output drivers to Hi-Z. Asynchronous Sleep Mode Input - Asserted (high) forces the SRAM into low-power mode. Read Operation Protocol Select - These mode pins must be tied to VDD or VSS before power-up. M1:M2 = 00 specifies Register - Flow Thru Read Operations M1:M2 = 01 specifies Register - Register Read Operations M1:M2 = 10 specifies Register - Latch Read Operations M1:M2 = 11 specifies Dual Clock Read Operations Output Impedance Control Resistor Input 3.3V Core Power Supply - Core supply voltage. Output Power Supply - Output buffer supply voltage. Input Reference Voltage - Input buffer threshold voltage. Ground
K, K C, C SS
Input Input Input
SW
Input
SBWa, SBWb, SBWc, SBWd
Input
G ZZ M1, M2
Input Input Input
ZQ VDD VDDQ VREF VSS TCK TMS TDI TDO NC
Input
Input Input Input Output
JTAG Clock JTAG Mode Select JTAG Data In JTAG Data Out No Connect - These pins are true no-connects, i.e. there is no internal chip connection to these pins. They can be left unconnected or tied directly to VDD or VSS.
4Mb, Sync LW, HSTL, rev 1.5
4 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB
Preliminary
BLOCK DIAGRAM
128K x 36 or 256K x 18 SA Reg.
^ Kint
Write Store Reg.
2:1 Mux
Address Dout Din Write Pulse 2:1 Mux
Output
Latch
DQ
Read Comp. Reg. SS Reg. Kint SW Reg. Kint SBW Reg. Kint Input Clock K/K C/C Output Clock Self Time Write Logic
^ ^ ^
Kint
M1 M2
Mode Control
G
4Mb, Sync LW, HSTL, rev 1.5
5 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB
Preliminary
*Truth Tables
Register - Register Mode
ZZ H L L L L L L SS (tn) X H L L L L L SW (tn) X X H H L L L SBWx (tn) X X X X L X H G X X H L X X X Mode Sleep (Power Down) Mode Deselect Read Read Write All Bytes Write Bytes With SBWx = L Abort Write DQ (tn) Hi - Z X Hi - Z X X X X DQ (tn+1) Hi - Z Hi - Z Hi - Z Q(tn) D(tn) D(tn) Hi - Z VDD Current ISB IDD IDD IDD IDD IDD IDD
Register - Latch and Register - Flow Thru Mode
ZZ H L L L L L L SS (tn) X H L L L L L SW (tn) X X H H L L L SBWx (tn) X X X X L X H G X X H L X X X Mode Sleep (Power Down) Mode Deselect Read Read Write All Bytes Write Bytes With SBWx = L Abort Write DQ (tn) Hi - Z Hi - Z Hi - Z Q(tn) Hi - Z Hi - Z Hi - Z DQ (tn+1) Hi - Z X Hi - Z X D(tn) D(tn) X VDD Current ISB IDD IDD IDD IDD IDD IDD
Dual Clock Mode
ZZ H L L L L L L SS (tn) X H L L L L L SW (tn) X X H H L L L SBWx (tn) X X X X L X H G X X H L X X X Mode Sleep (Power Down) Mode Deselect Read Read Write All Bytes Write Bytes With SBWx = L Abort Write DQ (tn) Hi - Z Hi - Z Hi - Z Q(tn) Hi - Z Hi - Z Hi - Z DQ (tn+1) Hi - Z X Hi - Z X D(tn) D(tn) Hi - Z VDD Current ISB IDD IDD IDD IDD IDD IDD
4Mb, Sync LW, HSTL, rev 1.5
6 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB
Preliminary
*Read Operations
These devices support four distinct JEDEC standard read protocols via mode pins M1 and M2. The mode pins must be set during power-up, and cannot change during SRAM operation. Mode Select Truth Table.
M1 Register - Register Register - Flow Thru Register - Latch Dual Clock L L H H M2 H L L H
When a read operation is initiated, all address and control signals (except G and ZZ) are latched into input registers on the rising edge of K clock. The latched address is decoded and then used to access a particular location in the internal memory array. These two events occur regardless which read protocol is selected. After the memory location is accessed, the read protocol determines when data from that memory location is driven valid externally. Register - Register Mode In Register - Register mode, data is driven valid externally from the subsequent rising edge of K clock, one full K clock cycle after the address is latched. Data remains valid until at least the next rising edge of K clock, one full K clock cycle thereafter. Register - Latch Mode In Register - Latch mode, data is driven valid externally from the subsequent falling edge of K clock, or, some minimum amount of time after the address is latched (determined by the access time of the memory array), whichever is greater. Data remains valid until at least the next falling edge of K clock, approximately one full K clock cycle thereafter. Register - Flow Thru Mode In Register - Flow Thru mode, data is driven valid immediately, some minimum amount of time after the address is latched (determined by the access time of the memory array). Data remains valid until at least the next rising edge of K clock, approximately one full K clock cycle thereafter. Dual Clock Mode In Dual Clock mode, data is driven valid from the subsequent rising edge of C clock, or, some minimum amount of time after the address is latched (determined by the access time of the memory array), whichever is greater. Data remains valid until at least the next rising edge of C clock, approximately one full C clock cycle thereafter. Regardless which read protocol is selected, read operations may be initiated consecutively, with no dead cycles between them.
4Mb, Sync LW, HSTL, rev 1.5
7 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB
Preliminary
*Write Operations
These devices follow a Late Write protocol, where, during a write operation, data is provided to the SRAM one clock cycle after the address and control signals, eliminating the need for one of the busturnaround cycles required when changing from a read to a write operation. The Late Write function is controlled internally by using a dedicated one-deep write buffer to store the address and data signals associated with the current write operation. The buffered data is not actually written to the memory array until the next write operation is initiated. When a write operation is initiated, all address and control signals (except G and ZZ) are latched into input registers on the rising edge of K clock. Also at this time, any valid data currently stored in the onedeep write buffer (associated with the previous write operation) is written to the memory array. On the subsequent rising edge of K clock, the data and address signals for the current write operation are stored in the write buffer. This write pipeline mechanism allows write operations to be initiated consecutively, with no dead cycles between them. Note: In order to maintain coherency, if a read operation is initiated to the same address as that of the last write operation (i.e. to the address of the write operation currently stored in the write buffer), read data is provided from the write buffer instead of the memory array. If only some of the bytes of data in the write buffer are valid, those bytes of data that are valid are provided from the write buffer, and those bytes of data that are invalid are provided from the memory array.
*Sleep (Power Down) Mode
Sleep (power down) mode is provided through the asynchronous input signal ZZ. When ZZ is asserted (high), the output drivers will go to a Hi-Z state, and the SRAM will begin to draw standby current. Contents of the memory array will be preserved. An enable time (tZZE) must be met before the SRAM is guaranteed to be in sleep mode, and a recovery time (tZZR) must be met before the SRAM can resume normal operation.
*Power-Up Sequence
Power supplies must power up in the following sequence: VSS, VDD, VDDQ, VREF, and Inputs. VDDQ must never exceed VDD.
*Programmable Impedance Output Drivers
These devices have programmable impedance output drivers. The output impedance is controlled by an external resistor, RQ, connected between the SRAM's ZQ pin and VSS, and is equal to one-fifth the value of this resistor. For output impedance matching within a 7.5% tolerance, RQ must be in the range of 100 to 200. For maximum output drive, the ZQ pin can be connected directly to VSS. For minimum output drive, the ZQ pin can be left open or connected to VDDQ. The output impedance is updated whenever the output drivers are in a Hi-Z state. At power up, 8192 clock cycles followed by a write or deselect operation are required to ensure that the output impedance has reached its desired value. After power up, periodic updates of the output impedance, via a write or deselect operation, are also required to ensure that the output impedance remains within a 7.5% tolerance.
4Mb, Sync LW, HSTL, rev 1.5
8 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB
Preliminary
*Absolute Maximum Ratings(1)
Item Supply Voltage Output Supply Voltage Input Voltage Output Voltage Operating Temperature Junction Temperature Storage Temperature Symbol VDD VDDQ VIN VOUT TA TJ TSTG Rating -0.5 to +4.6 -0.5 to +4.6 -0.5 to VDD+0.5 (4.6V max.) -0.5 to VDDQ+0.5 (4.6V max.) 0 to 85 0 to 110 -55 to 150 Unit V V V V
C C C
(1) Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
*PBGA Package Thermal Characteristics
Sample Form 1 JA PKG only Ambient Room Temp Air Flow (m/s) 0 1 2 3 0 1 2 3 0 1 2 3 Thermal Resistance (C/W) 81.0 36.9 29.5 26.1 32.4 23.8 20.7 18.6 16.0 12.9 12.0 11.3 3.6 Reference Max Thermal Resistance
2
JA
PKG on Board A*
Room Temp
*Board A is a two layer printed circuit board with very low density trace in both layers. **Board B is a four layer printed circuit board, same as Board A except with two GND planes in the middle layers. Min Thermal Resistance
3
JA
PKG on Board B**
Room Temp
4
JC
PKG only
DI Water
Board size & thickness (Board A, B): 7.62W x 11.43L x 1.57T (mm)
4Mb, Sync LW, HSTL, rev 1.5
9 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB
Preliminary (VSS = 0V, TA = 0 to 85oC)
*DC Recommended Operating Conditions
Item Supply Voltage Output Supply Voltage(1) Input Reference Voltage High Voltage(2) Low Voltage(3) Clock(4) Input Signal Voltage Differential Voltage Common Mode Voltage Cross Point Voltage B-Scan Input Input High Voltage(5) Input Low Voltage(5) Input High Voltage(6) Input Low Voltage(6) Output Impedance Control Resistor
(1) (2) (3) (4)
Symbol VDD VDDQ VREF VIH VIL VKIN VDIF VCM VX VTIHSC VTILSC VTIHBS VTILBS RQ
Min 3.13 1.4 0.5 VREF + 0.2 -0.3 -0.3 0.4 0.5 0.6 2.0 -0.3 VREF + 0.5 -0.3 100
Typ 3.3 ------------0.75 0.75 --------150
Max 3.47 1.6 1.0 VDD + 0.3 VREF - 0.2 VDD + 0.3 VDD + 0.6 1.1 1.0 VDD + 0.3 0.8 VDD + 0.3 VREF - 0.5 200
Unit V V V V V V V V V V V V V
Extended VDDQ support up to 2.0V is available - please contact marketing. VIH (Max) AC = V DD + 1.5V for pulse width less than 2.0 ns. VIL (Min) AC = -1.5V for pulse width less than 2.0 ns. These devices support two different input clocking schemes: a. Differential In this scheme, both clock inputs (K and K) are driven differentially. VKIN, VDIF, and VCM must all be considered when using this scheme.
b. Single Ended - In this scheme, one of the two clock inputs (either K or K) is driven to the same voltage levels as the other inputs, i.e. from VSS to VDDQ nominally, while the other clock input (either K or K) is tied to an external reference voltage (VX). VKIN, VDIF, and VX must all be considered when using this scheme.
(5) (6)
Scan control (SC) signals are: TDO, TDI, TMS & TCK. BS signals are all signals in the Boundary Scan chain except the scan control (SC) signals: TDO, TDI, TMS & TCK. (TA = 25oC, f = 1 MHz)
*I/O Capacitance
Item Input Capacitance Clock Input Capacitance Output Capacitance Symbol CIN CCLK COUT Test conditions VIN = 0V VIN = 0V VOUT = 0V Min -------
Max 6 6 7
Unit pF pF pF
Note: These parameters are sampled and are not 100% tested.
4Mb, Sync LW, HSTL, rev 1.5 10 / 33 July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB
Preliminary
*DC Electrical Characteristics
Item Input Leakage Current Output Leakage Current Power Supply Operating Current - x36 Symbol ILI ILO IDD-5.0 IDD-4.5 IDD-4.0 IDD-3.7 IDD-5.0 IDD-4.5 IDD-4.0 IDD-3.7 ISB VOH VOL ROUT1,2,3 Test Conditions VIN = VSS to VDD VOUT = VSS to VDD G = VIH IOUT = 0 mA SS = VIL, ZZ = VIL
(VDD = 3.3V 5%, VSS = 0V, TA = 0 to 85oC)
Min -1 -10 ---
Typ ----655 675 700 725 590 610 635 660 60 ----RQ/5
Max 1 10 ---
Unit uA uA mA
Power Supply Operating Current - x18
IOUT = 0 mA SS = VIL, ZZ = VIL
---
---
mA
Power Supply Standby Current Output High Voltage Output Low Voltage Output Driver Impedance
IOUT = 0 mA ZZ = VIH IOH = -6.0 mA RQ = 250 IOL = 6.0 mA RQ = 250 VOH = VDDQ/2 VOL = VDDQ/2
--VDDQ-0.4 --15
----0.4 50
mA V V
1. RQ needs to be in the range of 100 to 200 for proper control of the value of ROUT. 1.1 ROUT 15 when RQ 100 1.2 ROUT 50 when RQ 200 2. For maximum output drive, ZQ pin can be tied directly to VSS. The output impedance is as described in note 1.1. 3. For minimum output drive, ZQ pin can be no connect or tied to VDDQ. The output impedance is as described in note 1.2. 4. Typical IDD values measured at VDD=3.3V and TA = 25oC, with a 75% read / 25% write operation distribution.
4Mb, Sync LW, HSTL, rev 1.5
11 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB
Preliminary
*AC Electrical Characteristics (Register - Register Mode)
-37 Item Symbol Min Cycle Time Clock High Pulse Width Clock Low Pulse Width Address Setup Time Address Hold Time Write Enables Setup Time Write Enables Hold Time Synchronous Select Setup Time Synchronous Select Hold Time Data Input Setup Time Data Input Hold Time Clock High to Output Valid Clock High to Output Hold Clock High to Output Low-Z Clock High to Output High-Z Output Enable Low to Output Valid Output Enable Low to Output Low-Z Output Enable High to Output High-Z Sleep Mode Enable Time Sleep Mode Recovery Time tKHKH tKHKL tKLKH tAVKH tKHAX tWVKH tKHWX tSVKH tKHSX tDVKH tKHDX tKHQV tKHQX*2 tKHQX1*2 tKHQZ*2 tGLQV tGLQX*2 tGHQZ*2 tZZE*2 tZZR*2 3.45 1.3*3 1.3*3 0.3 1.0 0.3 1.0 0.3 1.0 1.0 1.0 --0.7 0.7 ----0.5 ----20.0 Max ----------------------2.25 ----2.25 2.25 --2.25 20.0 --Min 3.8 1.3*3 1.3*3 0.3 1.0 0.3 1.0 0.3 1.0 1.0 1.0 --0.7 0.7 ----0.5 ----20.0 Max ----------------------2.25 ----2.25 2.25 --2.25 20.0 --Min 3.8 1.5 1.5 0.3 1.0 0.3 1.0 0.3 1.0 1.0 1.0 --0.7 0.7 ----0.5 ----20.0 Max ----------------------2.25 ----2.25 2.25 --2.25 20.0 --Min 5.0 1.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 1.0 1.0 --0.7 0.7 ----0.5 ----20.0 Max ----------------------2.5 ----2.5 2.5 --2.3 20.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -38 -4 -45 Unit
1. All parameters are specified over the range TA = 0 to 85oC. 2. These parameters are sampled and are not 100% tested. 3. These parameters are characterized but not 100% tested at 1.3ns. They are 100% tested at 1.5ns.
4Mb, Sync LW, HSTL, rev 1.5
12 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB
Preliminary
*AC Electrical Characteristics (Register - Latch & Register - Flow Thru Modes)
-37 Item Symbol Min Cycle Time Clock High Pulse Width Clock Low Pulse Width Address Setup Time Address Hold Time Write Enables Setup Time Write Enables Hold Time Synchronous Select Setup Time Synchronous Select Hold Time Data Input Setup Time Data Input Hold Time Clock High to Output Valid Clock High to Output Hold (R-FT mode only) Clock High to Output Low-Z (R-FT mode only) Clock Low to Output Valid (R-L mode only) Clock Low to Output Hold (R-L mode only) Clock Low to Output Low-Z (R-L mode only) Clock High to Output High-Z Output Enable Low to Output Valid Output Enable Low to Output Low-Z Output Enable High to Output High-Z Sleep Mode Enable Time Sleep Mode Recovery Time tKHKH tKHKL tKLKH tAVKH tKHAX tWVKH tKHWX tSVKH tKHSX tDVKH tKHDX tKHQV tKHQX*2 tKHQX1*2 tKLQV tKLQX*2 tKLQX1*2 tKHQZ*2 tGLQV tGLQX*2 tGHQZ*2 tZZE*2 tZZR*2 4.8 1.5 1.5 0.4*3 0.8*3 0.4*3 0.8*3 0.4*3 0.8*3 1.0 0.8*3 --2.0 2.5 --0.7 0.7 ----0.5 ----20.0 Max ----------------------4.6 ----2.2 ----2.1 2.1 --2.1 20.0 --Min 4.8 1.5 1.5 0.4*3 0.8*3 0.4*3 0.8*3 0.4*3 0.8*3 1.0 0.8*3 --2.0 2.5 --0.7 0.7 ----0.5 ----20.0 Max ----------------------4.8 ----2.2 ----2.2 2.2 --2.2 20.0 --Min 5.2 1.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 1.0 1.0 --2.0 2.5 --0.7 0.7 ----0.5 ----20.0 Max ----------------------5.2 ----2.3 ----2.3 2.3 --2.3 20.0 --Min 6.0 1.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 1.0 1.0 --2.0 3.0 --0.7 0.7 ----0.5 ----20.0 Max ----------------------6.0 ----2.5 ----2.5 2.5 --2.3 20.0 --ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -38 -4 -45 Unit
1. All parameters are specified over the range TA = 0 to 85oC. 2. These parameters are sampled and are not 100% tested. 3. These parameters are measured from valid VIH/VIL levels to the clock mid-point. 4. R-FT mode operation is verified functionally, but associated timing parameters are guaranteed by design only and are not 100% tested.
4Mb, Sync LW, HSTL, rev 1.5
13 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB
Preliminary
*AC Electrical Characteristics (Dual Clock Mode)
-37 Item Symbol Min K Clock Cycle Time K Clock High Pulse Width K Clock Low Pulse Width C Clock Cycle Time C Clock High Pulse Width C Clock Low Pulse Width K to C Clock Delay C to K Clock Delay Address Setup Time Address Hold Time Write Enables Setup Time Write Enables Hold Time Synchronous Select Setup Time Synchronous Select Hold Time Data Input Setup Time Data Input Hold Time K Clock High to Output Valid C Clock High to Output Valid C Clock High to Output Hold C Clock High to Output Low-Z C Clock High to Output High-Z Output Enable Low to Output Valid Output Enable Low to Output Low-Z Output Enable High to Output High-Z Sleep Mode Enable Time Sleep Mode Recovery Time tKHKH tKHKL tKLKH tCHCH tCHCL tCLCH tKHCH tCHKH tAVKH tKHAX tWVKH tKHWX tSVKH tKHSX tDVKH tKHDX tKHQV tCHQV tCHQX*2 tCHQX1*2 tCHQZ*2 tGLQV tGLQX*2 tGHQZ*2 tZZE*2 tZZR*2 3.7 1.3*3 1.3*3 3.7 1.3*3 1.3*3 1.5 0.8 0.5 1.0 0.5 1.0 0.5 1.0 0.5 0.7 ----0.7 0.7 ----0.5 ----20.0 Max --------------------------------4.9 2.1 ----2.1 1.8 --1.8 20.0 --Min 3.8 1.3*3 1.3*3 3.8 1.3*3 1.3*3 1.5 0.8 0.5 1.0 0.5 1.0 0.5 1.0 0.5 0.7 ----0.7 0.7 ----0.5 ----20.0 Max --------------------------------4.9 2.1 ----2.1 1.8 --1.8 20.0 --Min 4.0 1.5 1.5 4.0 1.5 1.5 1.5 0.8 0.5 1.0 0.5 1.0 0.5 1.0 0.5 0.8 ----0.7 0.7 ----0.5 ----20.0 Max --------------------------------5.2 2.3 ----2.3 2.1 --2.0 20.0 --Min 4.5 1.5 1.5 4.5 1.5 1.5 1.5 0.8 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 ----0.7 0.7 ----0.5 ----20.0 Max --------------------------------6.0 2.5 ----2.5 2.5 --2.3 20.0 --ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -38 -4 -45 Unit
1. All parameters are specified over the range TA = 0 to 85oC. 2. These parameters are sampled and are not 100% tested. 3. These parameters are characterized but not 100% tested at 1.3ns. They are 100% tested at 1.5ns. 4. DC mode operation and timing parameters are tested in the CXK77B3640A only.
4Mb, Sync LW, HSTL, rev 1.5
14 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB
Preliminary
*AC Test Conditions (VDDQ = 1.5V)
(VDD = 3.3V 5%, VDDQ = 1.5V, TA = 0 to 85C)
Item Input Reference Voltage Input High Level Input Low Level Input Rise & Fall Time Input Reference Level Clock Input High Voltage Clock Input Low Voltage Clock Input Common Mode Voltage Clock Input Rise & Fall Time Clock Input Reference Level Output Reference Level Output Load Conditions
Symbol VREF VIH VIL
Conditions 0.75 1.25 0.25 1.0 0.75
Units V V V V/ns V V V V V/ns V V
Notes
VKIH VKIL VCM
1.25 0.25 0.75 1.0 K/K cross; C/C cross 0.75
VDIF 0.5V VDIF 0.5V
Fig.1 RQ = 250
Fig. 1: AC Test Output Load (VDDQ = 1.5V)
0.75 V 16.7 50 5 pF DQ 16.7 0.75 V 16.7 50 5 pF 50 50
4Mb, Sync LW, HSTL, rev 1.5
15 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB
Preliminary
*AC Test Conditions (VDDQ = 1.9V) .... for extended HSTL (R-L mode only)
(VDD = 3.3V 5%, VDDQ = 1.9V 0.1V, TA = 0 to 85C)
Item Input Reference Voltage Address / Control Input High Level Address / Control Input Low Level Data Input High Level Data Input Low Level Input Rise & Fall Time Input Reference Level Clock Input High Voltage Clock Input Low Voltage Clock Input Common Mode Voltage Clock Input Rise & Fall Time Clock Input Reference Level Output Reference Level Output Load Conditions
Symbol VREF VCAIH VCAIL VDIH VDIL
Conditions 0.85 1.45 0.35 1.25 0.55 1.0 0.85
Units V V V V V V/ns V V V V V/ns V V
Notes
VKIH VKIL VCM
1.45 0.75 1.1 1.0 K/K cross 0.95
VDIF = 0.7V VDIF = 0.7V
Fig.2 RQ = 250
Fig. 2: AC Test Output Load (VDDQ = 1.9V)
0.95 V 16.7 50 5 pF DQ 16.7 0.95 V 16.7 50 5 pF 50 50
4Mb, Sync LW, HSTL, rev 1.5
16 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB
Preliminary
Register - Register Mode
Timing Diagram of Read and Deselect Operations
K K
tKHKH tKHKL tKLKH
SA
n
tAVKH tKHAX
n+2
n+3
SW
tWVKH tKHWX
SS
tSVKH tKHSX tGLQV tGLQX
G
tKHQV tKHQX tGHQZ tKHQZ tKHQX1
DQ
Qn-2
Qn-1
Qn
Timing Diagram of Write Operations K K SA SS SW/SBWx G
tDVKH tKHDX
n
n+1
n+2
n+3
DQ
Dn-1
Dn
Dn+1
Dn+2
4Mb, Sync LW, HSTL, rev 1.5
17 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB
Preliminary
Register - Register Mode
Timing Diagram I of Read-Write-Read Operations (SS Controlled) K K SA SS SW/SBWx G = VIL DQ Read n Qn-1 Deselect Qn
tKHQZ
n
n+2
n+3
n+4
n+5
Dn+2 Write n+2 Read n+3
Qn+3 Read n+4
Timing Diagram II of Read-Write-Read Operations (G Controlled) K K SA SS = VIL SW/SBWx G DQ Read n Qn-1 Dummy Read n n+2 n+3 n+4 n+5
tGHQZ
Qn
Dn+2 Write n+2 Read n+3
Qn+3 Read n+4
4Mb, Sync LW, HSTL, rev 1.5
18 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB
Preliminary
Register - Latch Mode
Timing Diagram of Read and Deselect Operations
K K
tKHKH tKHKL tKLKH
SA
n
tAVKH tKHAX
n+1
n+3
SW
tWVKH tKHWX
SS
tSVKH tKHSX tKHQV tGLQV tGLQX
G
tKLQV tKLQX1 tKLQV tKLQX tGHQZ tKHQZ
DQ
Qn-1
Qn
Qn+1
Timing Diagram of Write Operations K K SA SS SW/SBWx G
tDVKH tKHDX
n
n+1
n+2
n+3
DQ
Dn-1
Dn
Dn+1
Dn+2
4Mb, Sync LW, HSTL, rev 1.5
19 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB
Preliminary
Register - Latch Mode
Timing Diagram of Read-Write-Read Operations K K SA SS SW/SBWx G = VIL DQ Read n
tKHQZ tKHQZ
n
n+1
n+2
n+4
n+5
Qn
Dn+1 Read n+2
Qn+2 Deselect Read n+4
Qn+4
Write n+1
4Mb, Sync LW, HSTL, rev 1.5
20 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB
Preliminary
Register - Flow Thru Mode
Timing Diagram of Read and Deselect Operations
K K
tKHKH tKHKL tKLKH
SA
n
tAVKH tKHAX
n+1
n+3
SW
tWVKH tKHWX
SS
tSVKH tKHSX tGLQV tGLQX
G
tKHQV tKHQX tGHQZ tKHQZ tKHQX1
DQ
Qn-1
Qn
Qn+1
Timing Diagram of Write Operations K K SA SS SW/SBWx G
tDVKH tKHDX
n
n+1
n+2
n+3
DQ
Dn-1
Dn
Dn+1
Dn+2
4Mb, Sync LW, HSTL, rev 1.5
21 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB
Preliminary
Register - Flow Thru Mode
Timing Diagram of Read-Write-Read Operations K K SA SS SW/SBWx G = VIL DQ Read n
tKHQZ tKHQZ
n
n+1
n+2
n+4
n+5
Qn
Dn+1 Read n+2
Qn+2 Deselect Read n+4
Qn+4
Write n+1
4Mb, Sync LW, HSTL, rev 1.5
22 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB
Preliminary
Dual Clock Mode
Timing Diagram of Read and Deselect Operations
K K
tKHKH tKHKL tKLKH
SA
n
tAVKH tKHAX
n+1
n+3
SW
tWVKH tKHWX
SS
tSVKH tKHSX
G
tGLQV tKHQV tCHQV tCHQX1 tCHQV tCHQX tGHQZ tGLQX tCHQZ
DQ
tCHKH
Qn-1
tKHCH
Qn
Qn+1
C C
tCHCH tCHCL tCLCH
4Mb, Sync LW, HSTL, rev 1.5
23 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB
Preliminary
Dual Clock Mode
Timing Diagram of Write Operations K K SA SS SW/SBWx G
tDVKH tKHDX
n
n+1
n+2
n+3
DQ
Dn-1
Dn
Dn+1
Dn+2
Timing Diagram I of Read-Write-Read Operations (SS Controlled) K K SA SS SW/SBWx G = VIL DQ C C Read n Deselect Write n+2 Read n+3 Read n+4 Qn
tCHQZ
n
n+2
n+3
n+4
n+5
Dn+2
Qn+3
Qn+4
4Mb, Sync LW, HSTL, rev 1.5
24 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB
Preliminary
Dual Clock Mode
Timing Diagram II of Read-Write-Read Operations (G Controlled) K K SA SS = VIL SW/SBWx G DQ C C Read n Dummy Read Write n+2 Read n+3 Read n+4 Qn
***Note*** (1)
n
n+2
n+3
n+4
n+5
tGHQZ
Dn+2
Qn+3
Qn+4
Note 1: In order to prevent glitches on the data bus during write-read operations, when G is driven active (low) following the rising edge of K, the data bus will remain tri-stated until valid data from the most recent read operation is available. Specifically, the data bus will remain tri-stated for the maximum of the following three times: 1.TKHQV 2.TKHCH + TCHQV 3.(K high to G low) + TGLQV
4Mb, Sync LW, HSTL, rev 1.5
25 / 33
July 23, 1998
SONY(R)
Test Mode Description
Functional Description
CXK77B3640AGB / CXK77B1840AGB
Preliminary
These devices provide a JTAG boundary scan interface using a limited set of IEEE std. 1149.1 functions. The test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller, etc.), SRAMs, other components and the printed circuit board. In conformance with a subset of IEEE std. 1149.1, these devices contain a TAP controller, Instruction register, Boundary Scan register and Bypass register. JTAG Inputs/Outputs are LVTTL compatible only. Test Access Port (TAP) 4 pins as defined in the Pin Description table are used to perform JTAG functions. The TDI input pin is used to scan test data serially into one of three registers (Instruction register, Boundary Scan register and Bypass register). TDO is the output pin used to scan test data serially out. The TDI pin sends the data into LSB of the selected register and the MSB of the selected register feeds the data to TDO. The TMS input pin controls the state transition of 16 state TAP controller as specified in IEEE std. 1149.1. Inputs on TDI and TMS are registered on the rising edge of TCK clock. The output data on TDO is presented on the falling edge of TCK. TDO driver is in active state only when TAP controller is in Shift-IR state or in Shift-DR state. TCK, TMS, TDI must be tied low when JTAG is not used. TAP Controller 16 state controller is implemented as specified in IEEE std. 1149.1. The controller enters reset state in one of two ways: 1. Power up. 2. Apply a logic 1 on TMS input pin on 5 consecutive TCK rising edges. Instruction Register (3 bits) The JTAG Instruction register consists of a shift register stage and parallel output latch. The register is 3 bits wide and is encoded as follow: Octal 0 1 2 3 4 5 6 7
4Mb, Sync LW, HSTL, rev 1.5
MSB..........LSB 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Instruction Bypass IDCODE. Read device ID Sample-Z. Sample Inputs and tri-state DQs Bypass Sample. Sample Inputs. Private. Manufacturer use only. Bypass Bypass
26 / 33 July 23, 1998
SONY(R)
Bypass Register (1 bit)
CXK77B3640AGB / CXK77B1840AGB
Preliminary
The Bypass Register is one bit wide and is connected electrically between TDI and TDO and provides the minimum length serial path between TDI and TDO. ID Registers (32 bits) The ID Register is 32 bits wide and is encoded as follows:
Device 128K x 36 256K x 18
Revision Number (31:28) xxxx xxxx
Part Number (27:12) 0000 0000 0001 1111 0000 0000 0010 0000
Sony ID (11:1) 0000 1110 001 0000 1110 001
Start Bit (0) 1 1
Boundary Scan Register (70 bits for 128Kx36, 51 bits for 256Kx18) The Boundary Scan Register contains the following bits:
128K x 36 DQ SA SW, SBWx SS, G K, K, C, C ZZ M1, M2 ZQ Place Holder 36 17 5 2 4 1 2 1 2 DQ SA
256K x 18 18 18 3 2 4 1 2 1 2
SW, SBWx SS, G K, K, C, C ZZ M1, M2 ZQ Place Holder
K/K, C/C inputs are sampled through one differential stage and inverted internally to generate internal K/K, C/C signals for scan registers. Place Holders are required for some NC pins to allow for future density upgrades, and are connected to VSS internally regardless of pin connection externally.
4Mb, Sync LW, HSTL, rev 1.5
27 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB 128K x 36 Scan Order Assignment (By Exit Sequence)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 5R 4P 4T 6R 5T 7T 6P 7P 6N 7N 6M 6L 7L 6K 7K 5L 4L 4K 4F 5G 7H 6H 7G 6G 6F 7E 6E 7D 6D 6A 6C 5C 5A 6B 5B M2 SA SA SA SA ZZ DQa DQa DQa DQa DQa DQa DQa DQa DQa SBWa K K G SBWb DQb DQb DQb DQb DQb DQb DQb DQb DQb SA SA SA SA NC SA SA NC SA SA SA SA DQc DQc DQc DQc DQc DQc DQc DQc DQc SBWc ZQ SS C C SW SBWd DQd DQd DQd DQd DQd DQd DQd DQd DQd SA SA SA M1 3B 2B 3A 3C 2C 2A 2D 1D 2E 1E 2F 2G 1G 2H 1H 3G 4D 4E 4G 4H 4M 3L 1K 2K 1L 2L 2M 1N 2N 1P 2P 3T 2R 4N 3R 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
Preliminary
Note: NC pins at pad locations 6B (#34) and 2B (#37) are connected to VSS internally, regardless of pin connection externally.
4Mb, Sync LW, HSTL, rev 1.5
28 / 33
July 23, 1998
SONY(R)
CXK77B3640AGB / CXK77B1840AGB 256K x 18 Scan Order Assignment (By Exit Sequence)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 5R 6T 4P 6R 5T 7T 7P 6N 6L 7K 5L 4L 4K 4F 6H 7G 6F 7E 6D 6A 6C 5C 5A 6B 5B M2 SA SA SA SA ZZ DQa DQa DQa DQa SBWa K K G DQb DQb DQb DQb DQb SA SA SA SA NC SA SA NC SA SA SA SA DQb DQb DQb DQb SBWb ZQ SS C C SW DQb DQb DQb DQb DQb SA SA SA SA M1 3B 2B 3A 3C 2C 2A 1D 2E 2G 1H 3G 4D 4E 4G 4H 4M 2K 1L 2M 1N 2P 3T 2R 4N 2T 3R 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
Preliminary
Note: NC pins at pad locations 6B (#24) and 2B (#27) are connected to VSS internally, regardless of pin connection externally.
4Mb, Sync LW, HSTL, rev 1.5
29 / 33
July 23, 1998
SONY(R)
Ordering Information.
CXK77B3640AGB / CXK77B1840AGB
Preliminary
Speed (Cycle Time / Access Time) Part Number
CXK77B3640A-37 CXK77B3640A-38 CXK77B3640A-4 CXK77B3640A-45 CXK77B1840A-37 CXK77B1840A-38 CXK77B1840A-4 CXK77B1840A-45
VDD
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
Size R-R
128K x 36 128K x 36 128K x 36 128K x 36 256K x 18 256K x 18 256K x 18 256K x 18 3.45ns / 2.25ns 3.8ns / 2.25ns 3.8ns / 2.25ns 5.0ns / 2.50ns 3.45ns / 2.25ns 3.8ns / 2.25ns 3.8ns / 2.25ns 5.0ns / 2.50ns
R-L & R-FT
4.8ns / 4.6ns 4.8ns / 4.8ns 5.2ns / 5.2ns 6.0ns / 6.0ns 4.8ns / 4.6ns 4.8ns / 4.8ns 5.2ns / 5.2ns 6.0ns / 6.0ns
DC
3.7ns / 4.9ns 3.8ns / 4.9ns 4.0ns / 5.2ns 4.5ns / 6.0ns ---------
Note: Contact Sony Memory Marketing for availability of DC mode functionality in CXK77B1840A.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
4Mb, Sync LW, HSTL, rev 1.5
30 / 33
July 23, 1998
SONY(R)
Revision History Rev. # rev 0.0 rev 0.0 Rev. date 02/10/98 02/20/98
CXK77B3640AGB / CXK77B1840AGB
Preliminary
Description of Modification Initial Version 1. Changed DC Recommended Operating Conditions (p. 10). 2. Added x36 and x18 typical IDD values (p. 11). 3. Changed 1.5V VDDQ AC Test Conditions (p. 15). 4. Changed 1.9V VDDQ AC Test Conditions (p. 16). 5. Added x36 and x18 part numbers in boundary scan ID Registers (p. 27). 1. Modified AC Timing Characteristics Renamed "-40" bin to "-4" bin in all modes. R-R Mode: Added "Clock Pulse Width timing parameters characterized but not 100% tested at 1.3ns" note for -37 and -38 bins. -37 TKHKH 4.0ns to 3.7ns TAVKH, TWVKH TSVKH 0.5ns to 0.3ns TKHQV, TKHQZ, TGLQV, TGHQZ 2.0ns to 2.25ns 4.0ns to 3.8ns -38 TKHKH TKHKL, TKLKH 1.4ns to 1.3ns TAVKH, TWVKH TSVKH 0.5ns to 0.3ns 2.1ns to 2.25ns TKHQV, TKHQZ, TGLQV, TGHQZ -4 TKHKH 4.5ns to 5.0ns TAVKH, TWVKH TSVKH 0.5ns to 0.3ns 2.3ns to 2.25ns TKHQV, TKHQZ, TGLQV, TGHQZ R-L, R-FT Modes: Added "Address, Control, and Data input setup and hold timing parameter measurement" note for -37 and -38 bins. Added "R-FT timing parameters guaranteed by design only" note for all bins. Removed TKHQZ1 from all bins. -37 TKHKL, TKLKH 1.3ns to 1.5ns TAVKH, TWVKH, TSVKH, TDVKH 0.5ns to 0.4ns TKHAX, TKHWX, TKHSX, TKHDX 1.0ns to 0.8ns TKHQV 5.0ns to 4.5ns TKLQV, TKHQZ, TGLQV, TGHQZ 2.0ns to 2.1ns -38 TKHKH 4.5ns to 5.0ns TKHKL, TKLKH 1.4ns to 1.5ns TAVKH, TWVKH, TSVKH, TDVKH 0.5ns to 0.4ns TKHAX, TKHWX, TKHSX, TKHDX 1.0ns to 0.8ns TKLQV, TKHQZ, TGLQV, TGHQZ 2.1ns to 2.2ns -4 TKHKH 5.0ns to 5.5ns -45 TKHKH 5.5ns to 6.0ns TKHQV 6.5ns to 6.0ns
rev 1.0
04/14/98
4Mb, Sync LW, HSTL, rev 1.5
31 / 33
July 23, 1998
SONY(R)
Rev. # rev 1.0 Rev. date 04/14/98
CXK77B3640AGB / CXK77B1840AGB Description of Modification
Preliminary
1. Modified AC Timing Characteristics (continued) DC Mode: Added "Clock Pulse Width timing parameters characterized but not 100% tested at 1.3ns" note for -37 and -38 bins. -37 TCHQV, TCHQZ 2.0ns to 2.1ns -38 TKHKL, TKLKH, TCHCL, TCLCH 1.4ns to 1.3ns TKHDX 0.8ns to 0.7ns TKHQV 5.1ns to 4.9ns TGLQV, TGHQZ 1.9ns to 1.8ns -4 TKHQV 5.3ns to 5.2ns -45 TKHQV 6.5ns to 6.0ns 2. Changed all maximum ambient temperature references (TA Max) from 70oC to 85oC (pp. 9-16). 1. Changed 1.9V VDDQ AC Test Conditions (p. 16). Deleted Input High and Low Levels. Added Address / Control Input High and Low Levels. Added Data Input High and Low Levels. Changed Input Reference Voltage (VREF) from 0.75V to 0.85V. 1. Changed VIH / VIL levels for Boundary Scan chain signals during Boundary Scan test mode (p. 10). 1. Modified AC Timing Characteristics R-R Mode: -4 TKHKH
rev 1.1
05/08/98
rev 1.2
05/18/98
rev 1.3
05/26/98
5.0ns to 3.8ns
rev 1.4
06/18/98
1. Modified AC Timing Characteristics R-R Mode: Changed TDVKH to 1.0ns in all bins. -37 TKHKH 3.7ns to 3.45ns R-L, R-FT Modes: Changed TDVKH to 1.0ns in all bins. -37 TKHKH 4.5ns to 4.8ns TKHQV 4.5ns to 4.6ns TKLQV 2.1ns to 2.2ns -38 TKHKH 5.0ns to 4.8ns TKHQV 5.0ns to 4.8ns -4 TKHKH 5.5ns to 5.2ns TKHQV 5.5ns to 5.2ns DC Mode: Added "DC operation and timing parameters tested in CXK77B3640A only" note for all bins.
4Mb, Sync LW, HSTL, rev 1.5
32 / 33
July 23, 1998
SONY(R)
Rev. # rev 1.5 Rev. date 07/23/98
CXK77B3640AGB / CXK77B1840AGB Description of Modification
Preliminary
1. Modified Output Driver Impedance (ROUT) section of DC Electrical Characteristics (p. 11). Changed "Min" and "Max" parameters to absolute values.
4Mb, Sync LW, HSTL, rev 1.5
33 / 33
July 23, 1998

▲Up To Search▲

Price & Availability of CXK77B1840AGB

	To Download CXK77B1840AGB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .